537 lines
15 KiB
Diff
537 lines
15 KiB
Diff
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diff --git a/src/pci-sysfs.c b/src/pci-sysfs.c
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new file mode 100644
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index 0000000..210bf40
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--- /dev/null
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+++ b/src/pci-sysfs.c
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@@ -0,0 +1,529 @@
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+/*
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+ * (C) Copyright IBM Corporation 2006
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+ *
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+ * Copyright (c) 2014-2018 NVIDIA Corporation
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+ *
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+ * All Rights Reserved.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a copy
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+ * of this software and associated documentation files (the "Software"), to deal
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+ * in the Software without restriction, including without limitation the rights
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+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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+ * copies of the Software, and to permit persons to whom the Software is
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+ * furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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+ * THE SOFTWARE.
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+ */
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+
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+/**
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+ * pcienum-sysfs.c
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+ *
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+ * Based on libpciaccess/src/linux_sysfs.c from libpciaccess-0.12.1, which was
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+ * found here:
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+ *
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+ * http://cgit.freedesktop.org/xorg/lib/libpciaccess
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+ *
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+ * Access PCI subsystem using Linux's sysfs interface. This interface is
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+ * available starting somewhere in the late 2.5.x kernel phase, and is the
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+ * preferred method on all 2.6.x kernels.
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+ *
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+ * Original author: Ian Romanick <idr@us.ibm.com>
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+ */
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+
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+#if defined(NV_LINUX)
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+
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+#include <stdlib.h>
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+#include <string.h>
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+#include <stdio.h>
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+#include <unistd.h>
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+#include <sys/types.h>
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+#include <sys/stat.h>
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+#include <fcntl.h>
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+#include <sys/mman.h>
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+#include <dirent.h>
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+#include <errno.h>
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+#include <sys/time.h>
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+#include <time.h>
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+#include <limits.h>
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+
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+#include "pci-enum.h"
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+#include "pci-sysfs.h"
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+
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+#define SYS_BUS_PCI "/sys/bus/pci/"
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+#define SYS_BUS_PCI_DEVICES SYS_BUS_PCI "devices"
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+#define SYS_BUS_PCI_RESCAN SYS_BUS_PCI "rescan"
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+#define PCI_DBDF_FORMAT "%04x:%02x:%02x.%1u"
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+#define SYSFS_PCI_BRIDGE_RESCAN_FMT SYS_BUS_PCI_DEVICES "/" PCI_DBDF_FORMAT "/rescan"
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+#define SYSFS_RESCAN_STRING "1\n"
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+#define SYSFS_RESCAN_STRING_SIZE 2
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+#define PCI_CAP_TTL_MAX 20
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+#define SYSFS_PATH_SIZE 256
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+
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+#define BAIL_ON_IO_ERR(buf, err, cnt, action) \
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+do { \
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+ if (((err) != 0) || ((cnt) < sizeof(buf))) \
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+ { \
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+ (err) = ((err) == 0) ? EIO : (err); \
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+ action; \
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+ } \
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+} while (0)
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+
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+static int pci_sysfs_read_cfg(uint16_t, uint16_t, uint16_t, uint16_t, uint16_t, void *,
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+ uint16_t size, uint16_t *);
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+
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+static int find_matches(struct pci_id_match *match);
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+
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+/**
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+ * Attempt to access PCI subsystem using Linux's sysfs interface to enumerate
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+ * the matched devices.
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+ */
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+int
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+pci_enum_match_id(struct pci_id_match *match)
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+{
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+ int err = 0;
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+ struct stat st;
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+
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+
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+ /*
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+ * If the directory "/sys/bus/pci/devices" exists, then the PCI subsystem
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+ * can be accessed using this interface.
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+ */
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+ match->num_matches = 0;
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+ if (stat(SYS_BUS_PCI_DEVICES, &st) == 0)
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+ {
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+ err = find_matches(match);
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+ }
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+ else
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+ {
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+ err = errno;
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+ }
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+
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+ return err;
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+}
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+
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+
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+/**
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+ * The sysfs lookup method uses the directory entries in /sys/bus/pci/devices
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+ * to enumerate all PCI devices, and then uses a file in each that is mapped to
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+ * the device's PCI config space to extract the data to match against.
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+ */
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+static int
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+find_matches(struct pci_id_match *match)
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+{
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+ struct dirent *d;
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+ DIR *sysfs_pci_dir;
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+ int err = 0;
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+
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+ sysfs_pci_dir = opendir(SYS_BUS_PCI_DEVICES);
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+ if (sysfs_pci_dir == NULL)
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+ {
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+ return errno;
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+ }
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+
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+ while ((d = readdir(sysfs_pci_dir)) != NULL)
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+ {
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+ uint8_t config[48];
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+ uint16_t bytes;
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+ unsigned dom, bus, dev, func;
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+ uint16_t vendor_id, device_id, subvendor_id, subdevice_id;
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+ uint16_t device_class;
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+
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+ /* Ignore the . and .. dirents */
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+ if ((strcmp(d->d_name, ".") == 0) || (strcmp(d->d_name, "..") == 0))
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+ {
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+ continue;
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+ }
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+
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+ sscanf(d->d_name, PCI_DBDF_FORMAT,
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+ & dom, & bus, & dev, & func);
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+
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+ err = pci_sysfs_read_cfg(dom, bus, dev, func, 0, config, 48, & bytes);
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+ if ((bytes == 48) && !err)
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+ {
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+ vendor_id = (uint16_t)config[0] + ((uint16_t)config[1] << 8);
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+ device_id = (uint16_t)config[2] + ((uint16_t)config[3] << 8);
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+ device_class = (uint16_t)config[10] +
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+ ((uint16_t)config[11] << 8);
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+ subvendor_id = (uint16_t)config[44] +
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+ ((uint16_t)config[45] << 8);
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+ subdevice_id = (uint16_t)config[46] +
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+ ((uint16_t)config[47] << 8);
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+
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+ /*
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+ * This logic, originally in common_iterator.c, will tell if
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+ * this device is a match for the search criteria.
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+ */
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+ if (PCI_ID_COMPARE(match->vendor_id, vendor_id) &&
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+ PCI_ID_COMPARE(match->device_id, device_id) &&
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+ PCI_ID_COMPARE(match->subvendor_id, subvendor_id) &&
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+ PCI_ID_COMPARE(match->subdevice_id, subdevice_id) &&
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+ ((device_class & match->device_class_mask) ==
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+ match->device_class))
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+ {
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+ match->num_matches++;
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+ }
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+ }
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+
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+ if (err)
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+ {
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+ break;
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+ }
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+ }
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+
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+ closedir(sysfs_pci_dir);
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+ return err;
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+}
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+
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+static int
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+pci_sysfs_read_cfg(uint16_t domain, uint16_t bus, uint16_t device,
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+ uint16_t function, uint16_t off, void *data,
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+ uint16_t size, uint16_t *bytes_read)
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+{
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+ char name[SYSFS_PATH_SIZE];
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+ uint16_t temp_size = size;
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+ int err = 0;
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+ int fd;
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+ char *data_bytes = data;
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+
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+ if (bytes_read != NULL)
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+ {
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+ *bytes_read = 0;
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+ }
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+
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+ /*
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+ * Each device has a directory under sysfs. Within that directory there
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+ * is a file named "config". This file used to access the PCI config
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+ * space. It is used here to obtain most of the information about the
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+ * device.
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+ */
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+ snprintf(name, SYSFS_PATH_SIZE - 1, "%s/" PCI_DBDF_FORMAT "/config",
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+ SYS_BUS_PCI_DEVICES, domain, bus, device, function);
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+
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+ fd = open(name, O_RDONLY);
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+ if (fd < 0)
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+ {
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+ return errno;
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+ }
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+
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+ if (off != 0)
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+ {
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+ if (lseek(fd, (off_t) off, SEEK_SET) < 0)
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+ {
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+ close(fd);
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+ return errno;
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+ }
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+ }
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+
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+ while (temp_size > 0)
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+ {
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+ const ssize_t bytes = read(fd, data_bytes, temp_size);
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+
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+ /*
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+ * If zero bytes were read, then we assume it's the end of the
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+ * config file.
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+ */
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+ if (bytes <= 0)
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+ {
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+ err = errno;
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+ break;
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+ }
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+
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+ temp_size -= bytes;
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+ data_bytes += bytes;
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+ }
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+
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+ if (bytes_read != NULL)
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+ {
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+ *bytes_read = size - temp_size;
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+ }
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+
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+ close(fd);
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+ return err;
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+}
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+
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+static int
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+pci_sysfs_write_cfg(uint16_t domain, uint16_t bus, uint16_t device,
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+ uint16_t function, uint16_t off, void *data,
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+ uint16_t size, uint16_t *bytes_written)
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+{
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+ char name[SYSFS_PATH_SIZE];
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+ uint16_t temp_size = size;
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+ int err = 0;
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+ int fd;
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+ char *data_bytes = data;
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+
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+ if (bytes_written != NULL)
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+ {
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+ *bytes_written = 0;
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+ }
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+
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+ /*
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+ * Each device has a directory under sysfs. Within that directory there
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+ * is a file named "config". This file used to access the PCI config
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+ * space.
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+ */
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+ snprintf(name, SYSFS_PATH_SIZE - 1, "%s/" PCI_DBDF_FORMAT "/config",
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+ SYS_BUS_PCI_DEVICES, domain, bus, device, function);
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+
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+ fd = open(name, O_WRONLY);
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+ if (fd < 0)
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+ {
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+ return errno;
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+ }
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+
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+ if (off != 0)
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+ {
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+ if (lseek(fd, (off_t) off, SEEK_SET) < 0)
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+ {
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+ close(fd);
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+ return errno;
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+ }
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+ }
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+
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+ while (temp_size > 0)
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+ {
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+ const ssize_t bytes = write(fd, data_bytes, temp_size);
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+
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+ if (bytes < 0)
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+ {
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+ err = errno;
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+ break;
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+ }
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+ /*
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+ * If zero bytes were written, then we assume it's the end of the
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+ * config file.
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+ */
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+ if (bytes == 0)
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+ {
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+ break;
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+ }
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+
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+ temp_size -= bytes;
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+ data_bytes += bytes;
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+ }
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+
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+ if (bytes_written != NULL)
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+ {
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+ *bytes_written = size - temp_size;
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+ }
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+
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+ close(fd);
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+ return err;
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+}
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+
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+int
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+pci_rescan(uint16_t domain, uint8_t bus, uint8_t slot, uint8_t function)
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+{
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+ char const *node;
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+ char node_buf[SYSFS_PATH_SIZE];
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+ int node_fd;
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+ ssize_t cnt;
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+
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+ if ((domain | bus | slot | function) == 0)
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+ {
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+ /* rescan the entire PCI tree */
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+ node = SYS_BUS_PCI_RESCAN;
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+ }
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+ else
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+ {
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+ snprintf(node_buf, sizeof(node_buf) - 1, SYSFS_PCI_BRIDGE_RESCAN_FMT,
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+ domain, bus, slot, function);
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+ node = node_buf;
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+ }
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+
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+ node_fd = open(node, O_WRONLY);
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+
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+ if (node_fd < 0)
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+ {
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+ return errno;
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+ }
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+
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+ cnt = write(node_fd, SYSFS_RESCAN_STRING, SYSFS_RESCAN_STRING_SIZE);
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+
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+ close(node_fd);
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+
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+ return cnt == SYSFS_RESCAN_STRING_SIZE ? 0 : EIO;
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+}
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+
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+int
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+pci_find_parent_bridge(pci_info_t *p_gpu_info, pci_info_t *p_bridge_info)
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+{
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+ char gpu_path[SYSFS_PATH_SIZE];
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+ char bridge_path[PATH_MAX];
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+ char *p_node;
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||
|
|
+
|
||
|
|
+ snprintf(gpu_path, SYSFS_PATH_SIZE - 1, "%s/" PCI_DBDF_FORMAT "/..", SYS_BUS_PCI_DEVICES,
|
||
|
|
+ p_gpu_info->domain, p_gpu_info->bus,
|
||
|
|
+ p_gpu_info->dev, p_gpu_info->ftn);
|
||
|
|
+
|
||
|
|
+ if (realpath(gpu_path, bridge_path) == NULL)
|
||
|
|
+ {
|
||
|
|
+ return errno;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ p_node = strrchr(bridge_path, '/');
|
||
|
|
+
|
||
|
|
+ if (p_node == NULL)
|
||
|
|
+ {
|
||
|
|
+ return ENOENT;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ ++p_node;
|
||
|
|
+
|
||
|
|
+ if (sscanf(p_node, PCI_DBDF_FORMAT,
|
||
|
|
+ &p_bridge_info->domain, &p_bridge_info->bus,
|
||
|
|
+ &p_bridge_info->dev, &p_bridge_info->ftn) != 4)
|
||
|
|
+ {
|
||
|
|
+ return ENOENT;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+static int
|
||
|
|
+pci_find_pcie_caps(uint16_t domain, uint8_t bus, uint8_t device, uint8_t ftn, uint8_t *p_caps)
|
||
|
|
+{
|
||
|
|
+ unsigned ttl;
|
||
|
|
+ uint8_t off;
|
||
|
|
+ uint8_t cap_id;
|
||
|
|
+ int err = ENXIO;
|
||
|
|
+ uint16_t cnt;
|
||
|
|
+
|
||
|
|
+ for (off = PCI_CAPABILITY_LIST, ttl = PCI_CAP_TTL_MAX; ttl; --ttl)
|
||
|
|
+ {
|
||
|
|
+ err = pci_sysfs_read_cfg(domain, bus, device, ftn, off,
|
||
|
|
+ &off, sizeof(off), &cnt);
|
||
|
|
+ BAIL_ON_IO_ERR(off, err, cnt, break);
|
||
|
|
+
|
||
|
|
+ /* Capabilities must reside above the std config header */
|
||
|
|
+ if ((off < PCI_STD_HEADER_SIZEOF) || (off == 0xff))
|
||
|
|
+ {
|
||
|
|
+ break;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ /* Clear the reserved bits */
|
||
|
|
+ off &= ~3;
|
||
|
|
+
|
||
|
|
+ err = pci_sysfs_read_cfg(domain, bus, device, ftn, off + PCI_CAP_LIST_ID,
|
||
|
|
+ &cap_id, sizeof(cap_id), &cnt);
|
||
|
|
+ BAIL_ON_IO_ERR(cap_id, err, cnt, break);
|
||
|
|
+
|
||
|
|
+ if (cap_id == PCI_CAP_ID_EXP)
|
||
|
|
+ {
|
||
|
|
+ goto found;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ if (cap_id == 0xff)
|
||
|
|
+ {
|
||
|
|
+ break;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ off += PCI_CAP_LIST_NEXT;
|
||
|
|
+ }
|
||
|
|
+ return err;
|
||
|
|
+found:
|
||
|
|
+ *p_caps = off;
|
||
|
|
+ return 0;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+int
|
||
|
|
+pci_bridge_link_set_enable(uint16_t domain, uint8_t bus, uint8_t device, uint8_t ftn, int enable)
|
||
|
|
+{
|
||
|
|
+ uint8_t pcie_caps = 0;
|
||
|
|
+ uint16_t reg;
|
||
|
|
+ uint32_t cap_reg;
|
||
|
|
+ uint16_t cnt;
|
||
|
|
+ int err;
|
||
|
|
+ struct timeval start;
|
||
|
|
+ struct timeval curr;
|
||
|
|
+ struct timeval diff;
|
||
|
|
+ struct timespec delay = {0, PCI_LINK_DELAY_NS};
|
||
|
|
+ struct timespec dlllar_disable_delay = {0, PCI_LINK_DLLLAR_DISABLE_DELAY_NS};
|
||
|
|
+
|
||
|
|
+ err = pci_find_pcie_caps(domain, bus, device, ftn, &pcie_caps);
|
||
|
|
+
|
||
|
|
+ if (err != 0)
|
||
|
|
+ {
|
||
|
|
+ return err;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ err = pci_sysfs_read_cfg(domain, bus, device, ftn, pcie_caps + PCI_EXP_LNKCTL,
|
||
|
|
+ ®, sizeof(reg), &cnt);
|
||
|
|
+ BAIL_ON_IO_ERR(reg, err, cnt, return err);
|
||
|
|
+
|
||
|
|
+ if (enable)
|
||
|
|
+ {
|
||
|
|
+ reg &= ~PCI_EXP_LNKCTL_LD;
|
||
|
|
+ }
|
||
|
|
+ else
|
||
|
|
+ {
|
||
|
|
+ reg |= PCI_EXP_LNKCTL_LD;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ err = pci_sysfs_write_cfg(domain, bus, device, ftn, pcie_caps + PCI_EXP_LNKCTL,
|
||
|
|
+ ®, sizeof(reg), &cnt);
|
||
|
|
+ BAIL_ON_IO_ERR(reg, err, cnt, return err);
|
||
|
|
+
|
||
|
|
+ if (enable)
|
||
|
|
+ {
|
||
|
|
+ /*
|
||
|
|
+ * Data Link Layer Link Active Reporting must be capable for
|
||
|
|
+ * zero power capable downstream port. But old controller might
|
||
|
|
+ * not implement it. In this case, we wait for 30 ms.
|
||
|
|
+ */
|
||
|
|
+ err = pci_sysfs_read_cfg(domain, bus, device, ftn, pcie_caps + PCI_EXP_LNKCAP,
|
||
|
|
+ &cap_reg, sizeof(cap_reg), &cnt);
|
||
|
|
+ BAIL_ON_IO_ERR(cap_reg, err, cnt, return err);
|
||
|
|
+
|
||
|
|
+ if (cap_reg & PCI_EXP_LNKCAP_DLLLARC)
|
||
|
|
+ {
|
||
|
|
+ /* wait for the link to go up and then sleep for 100 ms */
|
||
|
|
+
|
||
|
|
+ gettimeofday(&start, NULL);
|
||
|
|
+
|
||
|
|
+ for (;;)
|
||
|
|
+ {
|
||
|
|
+ err = pci_sysfs_read_cfg(domain, bus, device, ftn, pcie_caps + PCI_EXP_LNKSTA,
|
||
|
|
+ ®, sizeof(reg), &cnt);
|
||
|
|
+ BAIL_ON_IO_ERR(reg, err, cnt, return err);
|
||
|
|
+
|
||
|
|
+ if ((reg & PCI_EXP_LNKSTA_DLLLA) != 0)
|
||
|
|
+ {
|
||
|
|
+ break;
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ gettimeofday(&curr, NULL);
|
||
|
|
+ timersub(&curr, &start, &diff);
|
||
|
|
+
|
||
|
|
+ if ((diff.tv_sec > 0) || (diff.tv_usec >= PCI_LINK_WAIT_US))
|
||
|
|
+ {
|
||
|
|
+ return ETIME;
|
||
|
|
+ }
|
||
|
|
+ }
|
||
|
|
+ }
|
||
|
|
+ else
|
||
|
|
+ {
|
||
|
|
+ /*
|
||
|
|
+ * Measured the time on DGX1 for link to become established in a bridge,
|
||
|
|
+ * where the DLLLA reporting is supported and its approximately ~9ms,
|
||
|
|
+ * so wait for 30ms where DLLLA reporting is not supported.
|
||
|
|
+ */
|
||
|
|
+ PCI_NANOSLEEP(&dlllar_disable_delay, NULL);
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ PCI_NANOSLEEP(&delay, NULL);
|
||
|
|
+ }
|
||
|
|
+
|
||
|
|
+ return err;
|
||
|
|
+}
|
||
|
|
+
|
||
|
|
+#endif /* defined(NV_LINUX) */
|
||
|
|
\ No newline at end of file
|